VHDL untuk Rangkaian Penjumlah 1-Bit dalam FPGA

Half Adder

Penjumlahan biner dapat dilakukan sebagaimana berikut:

Menurut tabel kebenaran berbentuk,

A

B

Sum

Carry

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

Sum = A’.B + A.B’ = A xor B

Carry = A.B

Grafik dari penjumlah ini,

VHDL-nya:

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY halfadd IS

PORT ( A, B :   IN   STD_LOGIC ;

Sum, Cout :   OUT   STD_LOGIC ) ;

END;

ARCHITECTURE FungsiLogik OF halfadd IS

BEGIN

Sum <= A XOR B;

Cout <= A AND B;

END;

Full Adder

Biner penjumlah penuh,

Tabel Penjumlah penuh,

A

B Cin Sum

Cout

0

0 0 0 0

0

0 1 1

0

0

1 0 1 0

0

1 1 0

1

1

0 0 1

0

1

0 1 0

1

1 1 0 0

1

1 1 1 1

1

sehingga,

Sum = A xor B xor Cin

Cout = A.B + A.Cin + B.Cin

Grafik rangkaiannya,

Sehingga, program VHDL-nya,

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY fulladd IS

PORT ( Cin, A, B :   IN   STD_LOGIC ;

Sum, Cout :   OUT   STD_LOGIC ) ;

END;

ARCHITECTURE Fungsilogik OF fulladd IS

BEGIN

Sum <= A XOR B XOR Cin ;

Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;

END;

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